Yeah, it was very interesting. Though I sort of disagree about the non-temporal access part. Sure exposing the details of your cache hierarchy is stupid when that hierarchy can change. But telling the processor "I don't intend to access this data again" is actually a very useful hint for a lot of microarchitectures, and the ones that don't benefit can just ignore it (and even the cache-hierarchy specific ones can be either ignored or altered to suit a design -- none of them *promise* that data will be contained in a certain level of cache).
So he's absolutely right that exposing microarchitecture is generally a bad idea (and that IA-64 sucks), but there's still good to be had from memory usage hints. I think the main lesson here is not to get too specific on the ISA side, and on the programmer side don't get too wrapped up in trying to optimize "prefetch to L0/L1/L2" type instructions.
Great Read (Score:5, Informative)
Re:Great Read (Score:3)
Yeah, it was very interesting. Though I sort of disagree about the non-temporal access part. Sure exposing the details of your cache hierarchy is stupid when that hierarchy can change. But telling the processor "I don't intend to access this data again" is actually a very useful hint for a lot of microarchitectures, and the ones that don't benefit can just ignore it (and even the cache-hierarchy specific ones can be either ignored or altered to suit a design -- none of them *promise* that data will be contained in a certain level of cache).
So he's absolutely right that exposing microarchitecture is generally a bad idea (and that IA-64 sucks), but there's still good to be had from memory usage hints. I think the main lesson here is not to get too specific on the ISA side, and on the programmer side don't get too wrapped up in trying to optimize "prefetch to L0/L1/L2" type instructions.